1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a circuit and a method for generating a mode register set (MRS) code in a synchronous semiconductor memory device.
2. Description of the Related Art
A mode register and a mode register set (MRS) may be used in a synchronous semiconductor memory device. The mode register may program and store data for controlling various operational modes of a synchronous semiconductor memory device.
In a conventional memory device, operational modes and/or characteristics of a semiconductor memory device may be dictated by input signals. However, in a synchronous semiconductor memory device, an operational mode, i.e., a column address strobe (CAS) latency mode or a burst length mode, is normally determined beforehand, and thereafter the semiconductor memory device may be accessed. The operation mode is typically set and stored in the mode register as units of bits, and a group of such mode registers may be referred to as the MRS. Therefore, a series of codes indicating a mode of the semiconductor memory device may be set in the mode register set. These codes are often referred to as the MRS codes.
Conventionally, the MRS codes may be generated by combining addresses. The operation mode of the semiconductor memory device may be determined according to the generated MRS codes. The MRS codes are typically standard Joint Electron Device Engineering Council (JEDEC) codes.
An MRS code used to test a semiconductor memory device during design of the semiconductor memory device may be referred to as a test MRS code. The test MRS codes may be generated by combining addresses. However, test MRS codes are not standardized MRS codes; therefore, they are normally generated by combining certain addresses, while excluding other addresses. Accordingly, a limited number of test MRS codes may be generated.